In current semiconductor processing, as gate dimensions continue to get smaller, it is difficult to control critical dimensions CD. Critical dimensions are often controlled by spaced oxide deposition after lithography. If the spacer thickness is too thick, the gate cut reactive ion etching (RIE) might not be able to clear the polysilicon dummy gate electrode. Polysilicon residue at the bottom and corners of the cavities produced by gate cut RIE are affected by factors including gate open size, gate profile and gate height. Variability of these factors will lead to the polysilicon residuals causing tip-to-tip electrical shorts.
A need therefore exists for methodology enabling effective improvement of gate critical dimensions, mitigation of tip-to-tip shorts with effective residue removal, and effective improvement in device reliability, and the resulting device.